Formal Verification for High-Assurance Behavioral Synthesis Sandip Ray1 , Kecheng Hao2 , Yan Chen3 , Fei Xie2 , and Jin Yang4 1 Department of Computer Sciences, University of Texas at Austin, Austin, TX 78712

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Date: 2011-07-23 03:32:42 Electronic engineering Electronic design automation Design Formal methods Electronics Electronic design Formal equivalence checking Formal verification High-level synthesis Integrated circuit design Register-transfer level Invariant		Formal Verification for High-Assurance Behavioral Synthesis Sandip Ray1 , Kecheng Hao2 , Yan Chen3 , Fei Xie2 , and Jin Yang4 1 Department of Computer Sciences, University of Texas at Austin, Austin, TX 78712 Add to Reading List Source URL: www.mpi-sws.org Download Document from Source Website File Size: 362,73 KB Share Document on Facebook

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