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Date: 2004-03-21 14:53:16Formal equivalence checking Integrated circuit design Application-specific integrated circuit Logic synthesis Place and route Register-transfer level High-level synthesis Netlist Wire wrap Electronic engineering Electronic design automation Engineering Change Order | The Human ECO Compiler Steve GolsonAdd to Reading ListSource URL: www.trilobyte.comDownload Document from Source WebsiteFile Size: 240,37 KBShare Document on Facebook |