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Formal methods / Logic in computer science / NP-complete problems / And-inverter graph / Diagrams / Boolean satisfiability problem / Satisfiability / Logic synthesis / Automatic test pattern generation / Electronic engineering / Theoretical computer science / Electronic design automation


Improvements to Combinational Equivalence Checking Alan Mishchenko Satrajit Chatterjee Robert Brayton
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Document Date: 2006-08-09 21:17:37


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National Science Foundation / UC Berkeley / EECS University / University of California / Berkeley / U.S. Securities and Exchange Commission / United Nations / Combinational Equivalence Checking Alan Mishchenko Satrajit Chatterjee Robert Brayton Niklas Een Department / /

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W. H. Joyner / Jr. / Robert Brayton Niklas Een / Alan Mishchenko Satrajit Chatterjee Robert / A. Kuehlmann / V / Tim Cheng / Feng Lu / /

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