Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS ∗ Microprocessor Greg Semeraro1 , David Albonesi2 , Steven Dropsho3 , Grigorios Magklis3 , and Michael L. Scott3 1

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Date: 2003-11-09 18:03:42 Computer engineering CPU cache Cache Computer memory Alpha 21264 AMD 10h Microarchitecture Intel Core Pentium II Computer hardware Central processing unit Computer architecture		Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS ∗ Microprocessor Greg Semeraro1 , David Albonesi2 , Steven Dropsho3 , Grigorios Magklis3 , and Michael L. Scott3 1 Add to Reading List Source URL: www.cs.rochester.edu Download Document from Source Website File Size: 177,35 KB Share Document on Facebook

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