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City Austin / San Diego / / Company IBM / On-Chip Systems / 12th IEEE Intl / Multiple Datapath Resources / Transmeta Corporation / Managing Multi-Configuration Hardware / Intel / / / Facility Computer Science University of Rochester Rochester / Faster pipeline / Computer Engineering University of Rochester Rochester / Rochester Institute of Technology Rochester / / IndustryTerm control algorithms / set-associative cache energy / synchronous processor / clocked baseline processor / baseline processor / integer processing core / particular applications / real-time constraints / energy / queue control algorithm / transaction processing / metal / complexity adaptive processor / control algorithm / benchmark applications / technology file / energy dissipation / on-line adaption / adaptation algorithm / memory intensive applications / frame rate processing requirements / individual applications / deterministic algorithm / energy efficiency / aggressive superscalar processor / cross-product / multimedia applications / superscalar processors / / Organization Rochester Institute of Technology Rochester / National Science Foundation / Computer Science University of Rochester Rochester / Register Update Unit / UCSD / Electrical and Computer Engineering University of Rochester Rochester / ASIC / / Person H. Kaeslin / N. Felber / W. Fichtner / / / Position cache controller / controller / / ProgrammingLanguage FP / / ProvinceOrState New York / / PublishedMedium Microprocessor Report / / RadioStation With 32 / / Technology Alpha / aggressive superscalar processor / RAM / adaptation algorithm / complexity adaptive processor / jpeg / Locally Synchronous Processors / queue control algorithm / control algorithm / globally synchronous processor / aggressively clocked baseline processor / Operating Systems / adpcm / ASIC / control algorithms / ADAPTIVE CONTROL ALGORITHMS / Locally Synchronous SIMD Processor / GSM / Phase-Adaptive processors / simulation / Application Specific Processors / baseline processor / / SocialTag 
Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS ∗ Microprocessor Greg Semeraro1 , David Albonesi2 , Steven Dropsho3 , Grigorios Magklis3 , and Michael L. Scott3 1