National Semiconductors / Message Passing Systems / Prentice-Hall / LSI Logic / Sun Microsystems / Shared Virtual Memory Systems / Multiprocessor Systems / RAM1 / Stanford Computer Systems Laboratory / Aptix Inc. / Virtual Shared Memory Systems / RAM2 / Xilinx / /
Country
United Kingdom / /
Currency
AMD / / /
Event
FDA Phase / /
Facility
Systems University of Southern California Los Angeles / ASCII terminal / O port / building of RPM / /
IndustryTerm
interface tool / software system / schematic entry tool / synthesis tool / emulation systems / synthesis tools / parallel applications / software simulator decreases / level synthesis tools / cache cache protocol / inter-processor / identical systems / communication protocols / cache-coherent systems / directory-based cache protocol / target systems / software utilities / Software simulators / /
NaturalFeature
Instructions Multiple Data streams / /
Organization
National Science Foundation / MPS VSM / D3 D2 D1 D0 BOARD / CCLK BUF DEC F1 F2 SCSI HOST F7 CPU I/O Board / ASIC / Michel Dubois Department of Electrical Engineering / Systems University of Southern California Los Angeles / Delay Unit / FPGA Data/Clock Register D7 D6 CCLK BOARD / D4 D3 D2 D1 D0 BOARD / Stanford / /
Person
Anoop Gupta / Sasan Iman / Krishnan Ramamurthy / Jaswinder Pal Singh / Luiz A. Barroso / Michel Dubois / Wolf-Dietrich Weber / / /
Position
bus controller / FPGA Statistics Controller / MB FPGA2 First Level Cache Controller / distributed arbiter / second-level cache controller / Cypress CYM7232 DRAM controller / complex controller / Mbytes Memory Interleaving Registers DRAM Controller / controller / the control unit / FLC Status Control Unit Control Data Unit FPGA5 FPGA3 Controller / controller / programmer / /
Appeared in FPGA’95 The Design of RPM: An FPGA-based Multiprocessor Emulator Koray Öner, Luiz A. Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy and Michel Dubois Department of Electrical Engineering - System