230 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Optimality Study of Logic Synthesis for LUT-Based FPGAs - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Document - PDFSEARCH.IO - Document Search Engine

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	230 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Optimality Study of Logic Synthesis for LUT-Based FPGAs Add to Reading List Document Date: 2007-01-18 13:56:58 Open Document File Size: 895,88 KB Share Result on Facebook City San Francisco / Los Angeles / / Company IBM / ABC / VLSI CAD Laboratory / eASIC / Magma Design Automation Inc. / Xilinx Inc. / Get2Chip / AutoESL Design Technologies Inc. / abc/ Altera Inc. / Aplus Design Technologies Inc. / TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION SYSTEMS / Ultima Interconnect Technologies / Altera Corporation / Design / Circuits And Systems / Atrenta / Low Power Electronics / / Continent Asia / / Country China / / Currency USD / / / Event Reorganization / M&A / / Facility Microelectronics Center / University of Illinois / VLSI CAD Laboratory / Peking University / University of California / / IndustryTerm depthoptimal mapping solution / integrated technology mapping environment / technology-mapping problems / industrial tools / equivalent gate-level network / gatelevel network / near-optimal solutions / localized search algorithm / depth-optimal mapping solutions / logic synthesis algorithms / technology mapping algorithms / logicsynthesis algorithms / placement algorithms / binate-cover algorithm / synthesis algorithms / logic-optimization algorithms / programmable systems / synthesis tools / technology mapper / system-on-a-chip / logic-synthesis tool / logic-synthesis tools / placement tools / area-optimal technology mapping solution / decomposition algorithms / technology mapping solutions / technology mapping / synthesis systems / logic-synthesis algorithms / few novel algorithms / technology mapping solution / gate-level network / depth-optimal area optimization mapping algorithm / binate-covering solution / technology mapping algorithm / upper bound solutions / synthesis/mapping algorithms / createLEKO algorithm / technology-mapping algorithms / multilevel algorithm / Possible area-minimal mapping solutions / online community / logic synthesis tools / minimum-area technology mapping solution / / Organization Board of Governors of the IEEE Circuits / National Science Foundation / Systems Society / University of California / Berkeley / ACM/SIGDA Meritorious Service / Peking University / Beijing / University of Illinois / ACM SIGDA Advisory Board / University of California / Los Angeles / Microelectronics Center of North Carolina / Technical Advisory Board / / Person Y. Ding / R. Brayton / M. Ciesielski / J. Peck / Y. Hwang / Jason Cong / M. Xie / S. Brown / V / J. Shinnerl / J. Cong / G. Nataneli / J. Lin / A. Mishchenko / D. Chen / Kirill Minkovich Abstract / Kirill Minkovich / S. Chatterjee / M. Romesis / C. Wu / P. Pan / R. Aggarwal / V / E. Ding / K. Bazargan / / Position Editor / President / Chief Technology Advisor / Young Investigator / Professor and Chairman of the Computer Science Department / Professor / designer / / Product C5 / Adaptive Logic Module / / ProgrammingLanguage Verilog / / ProvinceOrState Illinois / North Carolina / California / / PublishedMedium IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS / / Technology FPGA / existing logic-optimization algorithms / synthesis algorithms / FPGA technology mapping algorithms / mapping algorithms / system-on-a-chip / logic synthesis algorithms / LUT FPGA technology mapping algorithm / SRAM / technology mapping algorithm / VHDL / INTEGRATED CIRCUITS / FPGA technology / Graph-based FPGA technology / integrated technology / previous algorithm / logic-synthesis algorithms / existing placement algorithms / Verilog / exiting synthesis algorithms / placement algorithms / localized search algorithm / existing logic-synthesis algorithms / FPGA synthesis/mapping algorithms / http / decomposition algorithms / area optimization mapping algorithm / FPGA synthesis algorithms / binate-cover algorithm / Digital Object Identifier / timing-driven placement algorithms / minimum-area technology / logicsynthesis algorithms / createLEKO algorithm / technology-mapping algorithms / / URL http / SocialTag Digital electronics Electronic design Integrated circuits Field-programmable gate array Logic synthesis Xilinx Logic optimization Jason Cong Algorithm Electronic engineering