Jason Cong

Results: 11



#Item
1FPGA’2013 Panel  Are FPGAs Suffering from the Innovator’s Dilemma? Moderator: Jason Cong, UCLA Panelists

FPGA’2013 Panel Are FPGAs Suffering from the Innovator’s Dilemma? Moderator: Jason Cong, UCLA Panelists

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Source URL: cadlab.cs.ucla.edu

- Date: 2013-02-19 20:09:58
    2An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu

    An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu

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    Source URL: www.bvsrc.org

    Language: English - Date: 2005-07-16 00:13:15
    3A Scalable, High-Performance Customized Priority Queue Muhuan Huang,* Kevin Lim+ and Jason Cong* * University of California, Los Angeles Computer Science Department

    A Scalable, High-Performance Customized Priority Queue Muhuan Huang,* Kevin Lim+ and Jason Cong* * University of California, Los Angeles Computer Science Department

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    Source URL: vast.cs.ucla.edu

    Language: English - Date: 2014-09-03 16:10:32
    4Accelerating Monte Carlo based SSTA Using FPGA Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan and Yi Zou Computer Science Department, University of California, Los Angeles Los Angeles, CA 9009

    Accelerating Monte Carlo based SSTA Using FPGA Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan and Yi Zou Computer Science Department, University of California, Los Angeles Los Angeles, CA 9009

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    Source URL: cadlab.cs.ucla.edu

    Language: English - Date: 2010-02-11 21:54:56
    5Microsoft Word - resume10.doc

    Microsoft Word - resume10.doc

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    Source URL: cadlab.cs.ucla.edu

    Language: English - Date: 2010-03-01 17:23:10
    6230  IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Optimality Study of Logic Synthesis for LUT-Based FPGAs

    230 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Optimality Study of Logic Synthesis for LUT-Based FPGAs

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    Source URL: cadlab.cs.ucla.edu

    Language: English - Date: 2007-01-18 13:56:58
    7Some	
  Professional	
  Highlights:	
  	
  2009-­‐present	
   Steven	
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    Some  Professional  Highlights:    2009-­‐present   Steven  Nowick  ([removed])     Below  is  a  list  of  some  highlight  in  the  last  5  years,  includi

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    Source URL: www.cs.columbia.edu

    Language: English - Date: 2014-08-10 17:10:46
    8A Fully Pipelined and Dynamically Composable Architecture of CGRA Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao and Peipei Zhou Computer Science Department University of California, Los Angeles Los Angeles, California,

    A Fully Pipelined and Dynamically Composable Architecture of CGRA Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao and Peipei Zhou Computer Science Department University of California, Los Angeles Los Angeles, California,

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    Source URL: vast.cs.ucla.edu

    Language: English - Date: 2014-04-13 17:33:49
    9Fabless semiconductor companies / Field-programmable gate array / Jason Cong / Logic synthesis / Altera / Application-specific integrated circuit / Special Interest Group on Design Automation / Computing with Memory / Synplicity / Electronic engineering / Electronics / Digital electronics

    Cell: ([removed]E-mail: [removed] Homepage: http://cadlab.cs.ucla.edu/~kirill/ Current Address: 5400 Lindley Ave #103 Encino, CA 91316

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    Source URL: cadlab.cs.ucla.edu

    Language: English - Date: 2010-03-01 17:22:48
    10Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs Jason Cong and Kirill Minkovich Computer Science Department University of California, Los Angeles Los Angeles, CA 90095, USA

    Improved SAT-Based Boolean Matching Using Implicants for LUT-Based FPGAs Jason Cong and Kirill Minkovich Computer Science Department University of California, Los Angeles Los Angeles, CA 90095, USA

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    Source URL: cadlab.cs.ucla.edu

    Language: English - Date: 2007-02-13 15:10:27