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Formal methods / Electronic design automation / Field-programmable gate array / Statistical static timing analysis / Static timing analysis / Standard cell / Application-specific integrated circuit / Integrated circuit design / Pattern matching / Electronic engineering / Electronics / Integrated circuits


Accelerating Monte Carlo based SSTA Using FPGA Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan and Yi Zou Computer Science Department, University of California, Los Angeles Los Angeles, CA 9009
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Document Date: 2010-02-11 21:54:56

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Monterey / Pattern Matching Pattern / /

Company

Mentor Graphics Corporation / ABC / RTL / GPU / BEEcube Inc. / Xilinx / Nvidia Corporation / /

Continent

Asia / /

Country

United States / /

Currency

pence / USD / /

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Facility

BEEcube Platform Studio / University of California / /

IndustryTerm

polynomial algorithm / technology scales / integrated technology mapping environment / incremental algorithm / software implementation / greedy algorithm / synthesis tool / pattern matching algorithm / optimized sharing solution / area optimization algorithm / manufacturing variations / Pattern selection algorithm / compilation tool / /

MarketIndex

MCNC / /

OperatingSystem

Linux / /

Organization

Yi Zou Computer Science Department / UC Berkeley / University of California / Los Angeles / /

Person

ISE VHDL / Wei Jiang / Jason Cong / Kirill Minkovich / /

Product

AutoPilot / BEE3 hardware platform / Xilinx ISE / FPGAs / BEE3 / /

ProgrammingLanguage

R / C / C++ / /

ProvinceOrState

California / /

Technology

integrated technology / FPGA / alternative SSTA algorithms / Linux / greedy algorithm / pattern matching algorithm / Pattern selection algorithm / Terms Algorithms / Integrated Circuits / incremental algorithm / polynomial algorithm / area optimization algorithm / /

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http /

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