IBM / Semiconductor Research Corporation / CEs / Accelerator-Based Systems / LMUs / Embedded Systems / STARnet / RTL / EURASIP Journal / Xilinx / Low Power Electronics / /
Continent
Asia / /
Currency
pence / AMD / / /
Facility
Peipei Zhou Computer Science Department University of California / A[j][k] B[j][k] Complex / Pipeline Initial Interval / Cluster Computation Complex / Computation Complex / /
IndustryTerm
system-on-chip / computation-intensive applications / compiler infrastructure / medical imaging / processor chips / bank switching / separate processing element / valid mapping solution / lowest energy consumption / on-chip data network / larger chips / work shares hardware / branch-and-bound algorithm / permutation network / pre-generated greedy solution / digital processing / reconfigurable computing architecture / energy benefits / energy savings / processor chip / smallest permutation network / target applications / energy / off-chip / energy consumption / energy efficiency improvement / bank / user applications / elegant solution / higher energy efficiency / memory bank / input applications / energy efficiency / detection algorithm / on-chip memory bank / data-parallel and computation-intensive applications / register chain / multimedia applications / word-level processing elements / /
Organization
National Science Foundation / GAM Synchronization Unit Global Data Transfer Unit / F. Global Data Transfer Unit / B. Local Memory Unit / Chiyuan Ma / Bingjun Xiao and Peipei Zhou Computer Science Department University / ASIC / Local Memory Unit / University of California / Los Angeles / Center for Domain-Specific Computing / Global Data Transfer Unit / /
A Fully Pipelined and Dynamically Composable Architecture of CGRA Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao and Peipei Zhou Computer Science Department University of California, Los Angeles Los Angeles, California,