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![]() Date: 2008-04-28 18:02:46Formal methods Logic in computer science Electronic design automation Mathematical logic Programming paradigms And-inverter graph Logic programming Model checking Boolean satisfiability problem Theoretical computer science Mathematics Applied mathematics | Add to Reading List |
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![]() | Scalable Logic Synthesis using a Simple Circuit Structure Alan Mishchenko Robert Brayton EECS Department, University of California, Berkeley, CA 94720DocID: O4NK - View Document |
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![]() | Verification after Synthesis Alan Mishchenko Robert Brayton Department of EECSDocID: O4H3 - View Document |
![]() | Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert BraytonDocID: O3JU - View Document |