The design of the control circuit for an asynchronous instruction prefetch unit using signal transition graphs S.-H. Chung and S.B. Furber Department of Computer Science, The University of Manchester, Oxford Road, Manche

Source URL: apt.cs.manchester.ac.uk

Preventing Synergistic Processor Element Indefinite Stalls Resulting from Instruction Depletion in the Cell Broadband Engine Processor for CMOS SOI 90 nm Applications Note

Source URL: cell.scei.co.jp

• Computing
• Cell
• Instruction prefetch
• Hazard
• Direct memory access
• Computer hardware
• Computer architecture
• Computer memory

Testing CPU Emulators Lorenzo Martignoni†‡ Roberto Paleari† Giampaolo Fresi Roglia† Danilo Bruschi† Dipartimento di Fisica‡ Università degli Studi di Udine Udine, Italy

Source URL: roberto.greyhats.it

• Central processing unit
• Emulator
• Instruction set
• QEMU
• MOV
• Bochs
• X86 architecture
• X86 assembly language
• Prefetch input queue
• Software
• Computer architecture
• System software

In Proceedings of the 4th International Symposium on High Performance Computing (ISHPC), May 2002, (c) Springer-Verlag. High Performance and Energy Efficient Serial Prefetch Architecture Glenn Reinman Brad Caldery

Source URL: cseweb.ucsd.edu

• Cache
• Computing
• Computer memory
• CPU cache
• Instruction prefetch
• Branch predictor
• Alpha 21264
• Microarchitecture
• Pentium Pro
• Computer hardware
• Computer architecture
• Central processing unit

PDF Document

Source URL: downloads.gamedev.net

• Assembly languages
• Compiler construction
• Data structure alignment
• Intel
• Protected mode
• MOV
• Instruction prefetch
• X86
• Addressing mode
• Computer architecture
• Computing
• Instruction set architectures

Prefetching using Markov Predictors Doug Joseph IBM T. J. Watson Research Lab

Source URL: www.ece.cmu.edu

• Computer architecture
• Central processing unit
• CPU cache
• Cache
• Prefetcher
• Prefetch buffer
• Instruction prefetch
• NOR flash replacement
• Computer memory
• Computer hardware
• Computing