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Interrupt descriptor table
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1	1 FROM RING3 TO RING0: EXPLOITING THE XEN X86 INSTRUCTION EMULATOR Andrei Vlad Luțaș Bitdefender Add to Reading List Source URL: labs.bitdefender.com Language: English - Date: 2016-01-22 04:06:36 Computer architecture Computing X86 architecture Interrupts X86 instructions Memory management Interrupt descriptor table Task state segment Global Descriptor Table Interrupt flag X86 Interrupt
2	The Page-Fault Weird Machine: Lessons in Instruction-less Computation Julian Bangert, Sergey Bratus, Rebecca Shapiro, Sean W. Smith Abstract not unique to either the x86 Memory Management Unit Add to Reading List Source URL: www.cs.dartmouth.edu Language: English - Date: 2013-09-11 09:08:25 Virtual memory Memory management Central processing unit Task state segment Global Descriptor Table X86 assembly language Protected mode Interrupt descriptor table Memory management unit Computer architecture X86 architecture Interrupts
3	src/sys/i386/i386/machdep Add to Reading List Source URL: vidstrom.net Language: English - Date: 2004-06-17 12:11:45 C programming language Interrupts C++ POSIX System call Interrupt descriptor table INT Exit X86 memory segmentation Computer architecture Computing X86 architecture
4	VIRUS BULLETIN www.virusbtn.com TECHNICAL FEATURE ANTI-UNPACKER TRICKS – PART THREE Peter Ferrie Add to Reading List Source URL: pferrie.host22.com Language: English - Date: 2011-09-27 16:43:27 Interrupts Debuggers SoftICE Assembly languages CPUID MOV INT Interrupt descriptor table JMP Computer architecture X86 instructions X86 architecture
5	Fiasco Kernel Debugger Manual Frank Mehnert Jan Glauber Jochen Liedtke Technische Universit¨at Dresden Add to Reading List Source URL: os.inf.tu-dresden.de Language: English - Date: 2010-09-10 06:00:42 Debuggers Debugging Breakpoint Program animation Interrupt descriptor table Kernel debugger Linux kernel Trap Ring Computing Computer architecture Software
6	White Paper Jenny M Pelner James A Pelner Firmware Architects Intel Corporation Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2011-09-21 13:35:07 X86 architecture Programming language implementation Booting Real mode Interrupt vector table Interrupt descriptor table Protected mode Intel APIC Architecture INT Computer architecture Interrupts BIOS
7	Application Note AN_324 FT900 User Manual Version 1.0 Issue Date: [removed] Add to Reading List Source URL: www.ftdichip.com Language: English - Date: 2014-11-10 18:08:33 Computing 8.3 filename Offset Processor register Transmission Control Protocol MD2 Memory address register Base address Interrupt descriptor table Computer memory Computer hardware Computer architecture
8	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:24:55 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86
9	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: support.amd.com Language: English - Date: 2013-11-01 16:14:30 X86 Interrupt descriptor table Task state segment Global Descriptor Table Protected mode CPUID Processor register Context switch INT Computer architecture X86 architecture Control register
10	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:25:06 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86

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