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SGI Origin / Integrated circuit design / Logic simulation / Standard cell / Verilog / Physical design / High-level synthesis / Synopsys / R10000 / Electronic engineering / Digital electronics / Electronic design automation
Date: 1999-02-05 11:20:10
SGI Origin
Integrated circuit design
Logic simulation
Standard cell
Verilog
Physical design
High-level synthesis
Synopsys
R10000
Electronic engineering
Digital electronics
Electronic design automation

Origin System Design Methodology and Experience: 1M-gate ASICs and Beyond Ásgeir Th. Eiríksson, John Keen, Alex Silbey, Swami Venkataraman, Michael Woodacre Silicon Graphics Inc., Mountain View, CA Abstract.

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