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Computer programming / OpenMP / Barrier / Thread / Scheduling / CPU cache / Computing / Concurrent computing / Parallel computing


Point-to-Point Synchronisation on Shared Memory Architectures J. Mark Bull and Carwyn Ball EPCC, The King’s Buildings, The University of Edinburgh, Mayfield Road, Edinburgh EH9 3JZ, Scotland, U.K. email:
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Document Date: 2007-10-15 03:40:58

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File Size: 75,91 KB

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City

Edinburgh / /

Company

IBM / the Sun / /

Country

United Kingdom / Scotland / /

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Facility

The University of Edinburgh / /

IndustryTerm

communication algorithm / system-specific solution / large shared memory systems / point-to-point algorithm / /

Organization

University of Edinburgh / /

Position

King / programmer / /

Technology

Power4 processor / eight processors / communication algorithm / 1.3 GHz Power4 processors / caching / 32 processors / Shared Memory / 900 MHz UltraSparc-III processors / 8 processors / 32 processor / API / point-to-point algorithm / eight processor / 52 processors / /

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