Memory data register - PDFSEARCH.IO - Document Search Engine

Memory data register
Results: 25

#	Item
1	Understanding POWER Multiprocessors Susmit Sarkar1 1 Peter Sewell1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English Computing Computer architecture Computer memory Concurrency Parallel computing Concurrent computing Memory barrier Synchronization Data dependency Microarchitecture Register renaming Memory model
2	Lecture 4: Modeling Sparse Matrix-Vector Multiply William Gropp www.cs.illinois.edu/~wgropp Sustained Memory Bandwidth Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2015-01-15 10:20:20 Computing Software engineering Central processing unit Computer programming Computer memory Cache Programming languages CPU cache Sparse matrix Processor register Fortran Data
3	Brewer’s Conjecture and the Feasibility of Consistent, Available, Partition-Tolerant Web Services Seth Gilbert∗ Nancy Lynch∗ Add to Reading List Source URL: www.comp.nus.edu.sg Language: English - Date: 2007-09-28 06:19:56 Transaction processing Computing Concurrent computing Data management Distributed computing ACID Consistency model Distributed shared memory Atomicity Consistency Consensus Shared register
4	The Semantics of Power and ARM Multiprocessor Machine Code Jade Alglave2 Anthony Fox1 Samin Ishtiaq3 Magnus O. Myreen1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Central processing unit Computer architecture Computer memory Parallel computing Instruction set architectures Memory barrier Processor register Instruction set ARM architecture ALGOL 68 CPU cache Computer data storage
5	Lecture 4: Modeling Sparse Matrix-Vector Multiply William Gropp www.cs.illinois.edu/~wgropp Sustained Memory Bandwidth Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2015-01-15 10:20:20 Central processing unit Computer memory Cache Programming languages CPU cache Sparse matrix Processor register Fortran Data
6	Microsoft PowerPoint - isc2015jiaolin Add to Reading List Source URL: isc2015.item.ntnu.no Language: English - Date: 2015-09-20 14:16:37 Cryptography Stream ciphers Grain Linear-feedback shift register Keystream Trade-off Time/memory/data tradeoff attack A5/1
7	Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches Alen Bardizbanyan† , Magnus Sj¨alander‡ , David Whalley‡ , and Per Larsson-Edefors† † Chalmers University of Technology, Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2013-11-15 06:28:01 Computer memory Cache CPU cache Translation lookaside buffer Lookup table Processor register Sum addressed decoder R8000 Computer hardware Central processing unit Computing
8	ATTACHMENT II MEMORY OF THE WORLD REGISTER FOR LATIN AMERICA AND THE CARIBBEAN APPLICATION FORM 2012 Add to Reading List Source URL: mowlac.files.wordpress.com Language: English - Date: 2012-08-02 15:12:38 Museology Art history Intellectual property law Libraries Memory of the World Programme UNESCO Preservation Provenance Copyright Archival science Information Data
9	IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 52, NO. 8, AUGUSTTABLE II OUR ATTACK COMPARED TO A GENERIC TIME/MEMORY/DATA TRADEOFF ATTACK Add to Reading List Source URL: www.cba.mit.edu Language: English - Date: 2011-12-13 18:32:02 Mathematics Cryptography Binary arithmetic Linear feedback shift register Pseudorandomness Stream cipher Information theory Factor graph Pseudorandom generator Pseudorandom number generators Theoretical computer science Applied mathematics
10	PDF Document Add to Reading List Source URL: edblog.hkedcity.net Language: English - Date: 2014-08-13 05:52:36 Computer engineering Instruction cycle Microarchitecture Instruction set Memory address Accumulator Memory data register Datapath Classic RISC pipeline Computer architecture Computer hardware Central processing unit

UPDATE