45nm High-k Metal Gate Strain-Enhanced Transistors C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, - Metal gate - Document - PDFSEARCH.IO

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	45nm High-k + Metal Gate Strain-Enhanced Transistors C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, Add to Reading List Document Date: 2009-09-12 14:10:53 Open Document File Size: 576,15 KB Share Result on Facebook City Hattendorf / / Company Ge / Intel Corp. / / / IndustryTerm metal-gates / metal-gate fill material / contact processing / dual-metal gates / metal / 65nm technology / metal gate transistors / 45nm technology node pitches / metal gate process / metal gate / mobility generation metal gate / 45nm logic technology / dual metal-gate / dual-metal process / metal gate technology / 45nm technology node / dual workfunction metal gate electrodes / dual-metal processing / excess metal / / / Technology 45nm logic technology / 65nm technology / lithography / metal gate technology / simulation / SRAM / dielectric / / SocialTag Electronics Silicon Logic families Digital electronics Semiconductor devices CMOS 45 nanometer Self-aligned gate Polycrystalline silicon Electronic engineering

45nm High-k + Metal Gate Strain-Enhanced Transistors C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris,Add to Reading List