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Mishchenko
Results: 82

#	Item
41	Improvements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-10-04 01:10:16 R-tree Static single assignment form Heuristic function Tree traversal Graph theory Tree decomposition Directed acyclic graph
42	Reducing Multi-Valued Algebraic Operations to Binary Jie-Hong R. Jiang Alan Mishchenko Robert K. Brayton Add to Reading List Source URL: www.bvsrc.org Language: Vietnamese - Date: 2002-12-06 20:56:43
43	Fast Minimum-Register Retiming via Binary Maximum-Flow Alan Mishchenko Aaron Hurst Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-11-20 10:30:53 Formal methods Electronics Retiming Electronic design automation Maximum flow problem Flow network Digital electronics Ford–Fulkerson algorithm Logic gate Network flow Electronic engineering Mathematics
44	SAT-Based Complete Don’t-Care Computation for Network Optimization Alan Mishchenko and Robert K. Brayton Department of EECS University of California, Berkeley {alanmi, brayton}@eecs.berkeley.edu Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2004-12-03 17:46:16 Boolean algebra Electronic design automation Formal methods Bioinformatics Boolean network Logic Boolean satisfiability problem Circuit Model checking Theoretical computer science Applied mathematics Mathematics
45	Logic Synthesis for Regular Layout using Satisfiability Marek Perkowski and Alan Mishchenko Department of Electrical and Computer Engineering Portland State University Portland, OR 97207, USA [mperkows, alanmi]@ece.pdx.e Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2002-05-01 01:40:28 Theoretical computer science Electronic design automation Diagrams Formal methods Lattice theory Binary decision diagram Boolean satisfiability problem Logic synthesis Lattice Abstract algebra Mathematics Boolean algebra
46	Optimization of Multi-Valued Multi-Level Networks M. Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa, and R. Brayton Electrical Engineering and Computer Sciences Dept. University of California, Ber Add to Reading List Source URL: www.bvsrc.org Language: English* - Date: 2004-06-17 16:08:02 Diagrams Model checking Many-valued logic Flip-flop Electronics Mathematics Mathematical logic Electronic engineering Binary decision diagram Boolean algebra
47	Improvements to Combinational Equivalence Checking Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-08-09 21:17:37 Formal methods Logic in computer science NP-complete problems And-inverter graph Diagrams Boolean satisfiability problem Satisfiability Logic synthesis Automatic test pattern generation Electronic engineering Theoretical computer science Electronic design automation
48	SAT-Based Complete Don’t-Care Computation for Network Optimization Alan Mishchenko Department of EECS University of California, Berkeley [removed] Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2004-04-30 02:47:03 Boolean algebra Computing Formal methods Electronic design automation Boolean satisfiability problem Boolean network Model checking Canonical form Lookup table Theoretical computer science Logic Mathematics
49	Fast Heuristic Minimization of Exclusive-Sums-of-Products∗ Alan Mishchenko and Marek Perkowski Department of Electrical and Computer Engineering Portland State University, Portland, OR 97207, USA [alanmi,mperkows]@ee.p Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2001-07-16 02:56:52 Electronic design Electronic design automation Boolean algebra Logic optimization Karnaugh map Logic synthesis Minimisation Cube Electronic engineering Design Digital electronics
50	A New Enhanced Constructive Decomposition and Mapping Algorithm Alan Mishchenko Xinning Wang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2003-03-28 23:46:48 Mathematics Binary decision diagram Model checking Computer programming Decomposition Lookup table Decomposition method Boolean algebra Computing Diagrams

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