Mishchenko

Results: 82



#Item
51Theoretical computer science / Conjunctive normal form / And-inverter graph / Science / Mathematics / Circuit / Canonical form / Boolean network / Logic / Electronic design automation / Formal methods

Applying Logic Synthesis for Speeding Up SAT Niklas Een, Alan Mishchenko, Niklas S¨ orensson Cadence Berkeley Labs, Berkeley, USA. EECS Department, University of California, Berkeley, USA. Chalmers University of Technol

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Language: English - Date: 2007-03-20 02:33:25
52Electronic design automation / Boolean network / Science / Mathematics / Design / Diagrams / Formal methods / And-inverter graph

SAT-Based Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang

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Language: English - Date: 2007-04-23 22:32:02
53Boolean algebra / Diagrams / Field-programmable gate array / Binary decision diagram / Lookup table / Xilinx / Multiplexer / Artificial neuron / Function / Computing / Mathematics / Electronic engineering

LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan

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Language: English - Date: 2009-07-09 02:20:06
54Counterexample / Abstract art / Mind / Culture / Visual arts / Abstraction / Model checking

A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction Niklas Een, Alan Mishchenko Nina Amla

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Language: English - Date: 2010-08-11 17:54:26
55Digital typography / Western calligraphy / Calligraphy / Collation / Latin-derived alphabet / World glyph set / Latin alphabets / Character encoding / Latin script

On Breakable Cyclic Definitions Jie-Hong R. Jiang, Alan Mishchenko, and Robert K. Brayton Department of Electrical Engineering and Computer Sciences University of California, Berkeley ABSTRACT

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Language: English - Date: 2005-05-01 20:25:39
56Applied mathematics / And-inverter graph / Electronic design automation / Subgraph isomorphism problem / Automatic test pattern generation / Graph isomorphism / Theoretical computer science / Mathematics / Diagrams

Incremental Sequential Equivalence Checking and Subgraph Isomorphism Sayak Ray Alan Mishchenko Robert Brayton

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Language: English - Date: 2009-07-12 14:37:50
57Logic synthesis / Circuit / Standard cell / Boolean function / Electronic engineering / Electronic design automation / And-inverter graph

Technology Mapping with Boolean Matching, Supergates and Choices Alan Mishchenko Satrajit Chatterjee Robert Brayton

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Language: English - Date: 2006-04-19 22:57:46
58Electronic design automation / Digital electronics / Logic in computer science / Electrical circuits / And-inverter graph / Retiming / Automatic test pattern generation / Formal verification / Combinational logic / Electronic engineering / Formal methods / Theoretical computer science

Scalably-Verifiable Sequential Synthesis Robert Brayton Alan Mishchenko Department of EECS, University of California, Berkeley

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Language: English - Date: 2007-10-02 14:31:33
59Graph connectivity / Diagrams / Models of computation / Directed acyclic graph / Transitive closure / Reachability / Unreachable memory / Model checking / Connected component / Graph theory / Mathematics / Theoretical computer science

Inductively Finding a Reachable State Space Over-Approximation Michael L. Case Alan Mishchenko

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Language: English - Date: 2006-05-01 16:01:54
60Boolean algebra / Algebraic logic / Diagrams / Computability theory / Binary decision diagram / Model checking / Indicator function / Recursion / Function / Mathematics / Mathematical logic / Mathematical analysis

An Introduction to Zero-Suppressed Binary Decision Diagrams Alan Mishchenko Department of Electrical and Computer Engineering Portland State University, Portland, OR 97207, USA [removed]; http://www.ee.pdx.edu/~a

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Language: English - Date: 2001-09-30 22:57:32
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