Date: 2012-07-23 18:26:39Physical design Multiple patterning Design closure Cadence Design Systems Design flow Placement Standard cell Routing Nanoroute Electronic engineering Electronic design automation Signoff | | Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factor. 40nm chips are state-of-the-art, 3Add to Reading ListSource URL: www.cadence.comDownload Document from Source Website File Size: 396,35 KBShare Document on Facebook
|