LiPo Li2 Poly Li1 Active (+) Metal / V0 Li2 Li1 Active (+) Metal / Lg / Active Metal 1 V0 Li2 Li1 Metal / V0 Li2 Li1 Metal 1 V0 Metal / Cadence Design Systems Inc. / /
Facility
Encounter Power System / /
IndustryTerm
Internet access / double-patterning technology / metal / high-k metal gate / wireless space / clock network / technology helps / graphics processors / electronics industry / metal shapes / Metal pitches / consumer devices / cell metal shapes / manufacturing flow / manufacturing / computing / 20nm process technology / clock networks / metal layers / low-power chips / 40nm chips / 20nm manufacturing requirements / signoff solution / /
Position
intent forward / rule-driven layout editor / /
Product
Encounter / 20nm / /
ProgrammingLanguage
DC / /
Technology
semiconductor / 20nm process technology / graphics processors / double-patterning technology / smartphones / design verification system / lithography / simulation / low-power chips / PDF / /
Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factor. 40nm chips are state-of-the-art, 3