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Multiprocessor
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131	Multiprocessor task scheduling in multistage hybrid ﬂow-shops: a genetic algorithm approach F Sivrikaya S¸erifog˘lu1* and G Ulusoy2 1 Abant Izzet Baysal University, Bolu, Turkey; 2Sabanci University, Istanbul, Turke Add to Reading List Source URL: research.sabanciuniv.edu Language: English - Date: 2011-09-30 05:03:31 Mathematics Planning Scheduling Mathematical sciences Job shop scheduling Theoretical computer science Genetic algorithm Algorithm Multiprocessor scheduling Operations research Mathematical optimization Applied mathematics
132	T HESIS FOR THE D EGREE OF D OCTOR OF P HILOSOPHY Three Aspects of Real-Time Multiprocessor Scheduling: Timeliness, Fault Tolerance, Mixed Criticality Add to Reading List Source URL: www.cse.chalmers.se Language: English - Date: 2012-10-19 09:59:57 Planning Real-time computing Multiprocessor scheduling Fault-tolerant design Computing Technology Mathematical sciences Scheduling algorithms Scheduling Operations research
133	T HESIS FOR THE D EGREE OF D OCTOR OF P HILOSOPHY Three Aspects of Real-Time Multiprocessor Scheduling: Timeliness, Fault Tolerance, Mixed Criticality Add to Reading List Source URL: www.cse.chalmers.se Language: English - Date: 2012-10-19 09:59:57 Planning Real-time computing Multiprocessor scheduling Fault-tolerant design Computing Technology Mathematical sciences Scheduling algorithms Scheduling Operations research
134	Three Aspects of Real-Time Multiprocessor Scheduling: Timeliness, Fault Tolerance, Mixed Criticality Risat Mahmud Pathan Department of Computer Science and Engineering Chalmers University of Technology, Sweden Add to Reading List Source URL: www.cse.chalmers.se Language: English - Date: 2012-10-12 10:39:13 Operations research Planning Multiprocessor scheduling Fault-tolerant design Technology Computing Mathematical sciences Earliest deadline first scheduling Rate-monotonic scheduling Scheduling algorithms Scheduling Real-time computing
135	Provably Efficient Two-Level Adaptive Scheduling Yuxiong He1 , Wen-Jing Hsu1 , and Charles E. Leiserson2 1 Nanyang Technological University, Nanyang Avenue[removed], Singapore, Add to Reading List Source URL: supertech.csail.mit.edu Language: English - Date: 2014-09-16 08:27:51 Computing Planning Job shop scheduling Multiprocessor scheduling Applied mathematics Thread Job scheduler Parallel computing Operations research Scheduling Mathematical optimization
136	Exploring a Multiprocessor Design Space to Analyze the Impact of Using STT-RAM in the Memory Hierarchy A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA Add to Reading List Source URL: conservancy.umn.edu Language: English - Date: 2014-12-17 15:49:56 Digital media Magnetoresistive random access memory Random-access memory CPU cache Memory hierarchy Benchmark Cell Computer memory Computer hardware Computing
137	Process Sleep and Wakeup on a Shared-memory Multiprocessor Rob Pike Dave Presotto Ken Thompson Gerard Holzmann Add to Reading List Source URL: plan9.bell-labs.com Language: English - Date: 2007-04-15 17:41:14 Concurrent computing Rendezvous Test-and-set Interrupt Linearizability Sleep Lock Mutual exclusion Spinlock Concurrency control Computer architecture Computing
138	Multiprocessor Support for Event-Driven Programs Nickolai Zeldovich∗, Alexander Yip, Frank Dabek, Robert T. Morris, David Mazi`eres†, Frans Kaashoek [removed], {yipal, fdabek, rtm, kaashoek}@lcs.mit.ed Add to Reading List Source URL: people.csail.mit.edu Language: English Classes of computers Callback Subroutines Asynchronous I/O Cache Multiprocessing Pin FreeBSD Server Computing Concurrent computing Parallel computing
139	— IEEE Transactions on Signal Processing, Vol. 45, No. 6, June 1997 — OPTIMIZING SYNCHRONIZATION IN MULTIPROCESSOR DSP SYSTEMS Shuvra S. Bhattacharyya, Sundararajan Sriram, and Edward A. Lee February 11, 1997 Add to Reading List Source URL: ptolemy.eecs.berkeley.edu Language: English - Date: 1997-08-12 13:24:54 Graph Directed graph Graph theory Mathematics Theoretical computer science
140	A Simulation Framework for Multiprocessor SoCs by Integrating SystemC with High-Level Processor Models Somasundaram Meiyappan HT023601A School of Computing National University of Singapore Add to Reading List Source URL: www.webabode.com Language: English - Date: 2013-12-10 10:54:58 Hardware description languages Logic design Simulation software SystemC Parallel computing System on a chip VHDL Simulation Logic simulation Electronic engineering Digital electronics Electronic design automation