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Digital media / Magnetoresistive random access memory / Random-access memory / CPU cache / Memory hierarchy / Benchmark / Cell / Computer memory / Computer hardware / Computing


Exploring a Multiprocessor Design Space to Analyze the Impact of Using STT-RAM in the Memory Hierarchy A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA
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Document Date: 2014-12-17 15:49:56

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File Size: 723,34 KB

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Company

Write Pulse Width Trade / Kia / /

Facility

University of Minnesota / /

IndustryTerm

memory technologies / spin-tronic technology / energy / /

Organization

GRADUATE SCHOOL / Functional Unit / UNIVERSITY OF MINNESOTA / /

Person

Swati Borse / David J. Lilja / Cong Ma / William Tuohy / Pushkar Borse / William Cooper / Ashok Borse / /

Position

advisor / /

ProvinceOrState

Minnesota / /

Technology

Cache Memory / spin-tronic technology / memory technologies / RAM / 3.2 Simulated Annealing Algorithm / 25 4.2 Processor / SRAM / Simulation / promising technology / 1.4 Simulated Annealing Algorithm / /

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