Exploring a Multiprocessor Design Space to Analyze the Impact of Using STT-RAM in the Memory Hierarchy A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA

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Date: 2014-12-17 15:49:56 Digital media Magnetoresistive random access memory Random-access memory CPU cache Memory hierarchy Benchmark Cell Computer memory Computer hardware Computing		Exploring a Multiprocessor Design Space to Analyze the Impact of Using STT-RAM in the Memory Hierarchy A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA Add to Reading List Source URL: conservancy.umn.edu Download Document from Source Website File Size: 723,34 KB Share Document on Facebook

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