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Central processing unit / Computer architecture / CPU cache / Cache / Oram / Dynamic random-access memory / B-tree / Microarchitecture / Computer hardware / Computer memory / Computing


Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors Ling Ren, Xiangyao Yu, Christopher W. Fletcher ∗, Marten van Dijk and Srinivas Devadas MIT CSAIL, Cambridge, MA, USA {renling, yxy, c
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Document Date: 2013-04-22 20:42:08

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File Size: 2,78 MB

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City

Tel-Aviv / /

Company

AES / Aegis / /

Country

United States / Israel / /

Currency

USD / AMD / /

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Facility

store AESK / Building Path ORAM / /

IndustryTerm

secure processor / off-chip / secure processors / normal processor / client algorithm / tamper-resistant processors / insecure processor / cloud computing / conventional processor / medical diagnosis software / processor chip / /

MarketIndex

SPEC / /

Organization

National Science Foundation / MIT / US Federal Reserve / Department of Defense / SESC / /

Person

Christopher W. Fletcher / Marten van Dijk / Srinivas Devadas / /

/

Position

official US policy / forward / memory controller / /

Product

Path ORAM / DRAMSim2 / OTPs / /

ProgrammingLanguage

FP / /

ProvinceOrState

Manitoba / /

PublishedMedium

on SPEC / /

RadioStation

10 Core / /

Technology

encryption / Ascend secure processor / RAM / previous secure processors / conventional processor / tamper-resistant processors / 2.2 Randomized Encryption / secure processor / insecure processor / processor chip / secret key / counter-based randomized encryption / trusted processor / trusted ORAM client algorithm / normal processor / /

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