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Computer hardware / C-slowing / Field-programmable gate array / Parallel computing / Retiming / Processor register / Cell / Classes of computers / Electronic engineering / Computer architecture / Central processing unit


Exploration of RaPiD-style Pipelined FPGA Interconnects Akshay Sharma1, Katherine Compton2, Carl Ebeling3, Scott Hauck1
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Document Date: 2005-07-19 18:43:06

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File Size: 297,08 KB

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City

Madison / Seattle / /

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Facility

University of Washington / We pipeline / O terminal / University of Wisconsin / /

IndustryTerm

digital camera imaging pipeline / reconfigurable computing / simplistic router / architecture independent algorithm / area-delay product / area-delay products / reconfigurable technologies / areadelay product / compute-intensive applications / pre-processing heuristic / signal processing tasks / architecture generation tool / placement algorithm / interconnect site / reconfigurable device / local register bank / register bank / encryption chip / reconfigurable systems / /

Movie

At first sight / /

Organization

University of Washington / University of Wisconsin / /

Position

representative / /

ProgrammingLanguage

Verilog / /

ProvinceOrState

Wisconsin / British Columbia / Washington / /

Technology

encryption / FPGA / encryption chip / RAM / Verilog / I/O protocol / PipeRoute algorithm / Pathfinder algorithm / SRAM / virtual memory / 1-Register router / DSP / placement algorithm / digital camera / CAD / routed using the PipeRoute algorithm / /

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