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City Saint-Malo / / Company Frontend App Server FPINT Conv Bank / ProtoFlex / SODIMM Bank / Tag Bank / Timing Model Config Reg Bank / QoS DRAM Timing DDR2 Memory / RTL / Xilinx / / Country France / / Currency USD / / / Event Business Partnership / Reorganization / Person Communication and Meetings / / Facility FPGA pipeline / Fort et al. / Wisconsin Wind Tunnel / University of California / / IndustryTerm tool chain / software thread interleavings change depending / financial simulation media encoder / manycore processors / page-coloring algorithm / target processors / point-to-point network / software synchronization / parallel software runtime / memory network / out-of-order superscalar processors / software porting / emulation systems / mechanism to prevent applications / sufficient hardware / parallel systems / on-chip routers / final target technology / lowest energy / ubiquitous parallel processing / energy / interaction between hardware / target processor / Parallel applications / system software co-design / on-chip interconnection network / software functional model / sequential software simulators / target hardware / bank / shared simulator infrastructure / gate-level emulation products / software interactions / software simulator / target systems / software simulators / out-oforder superscalar processor / / MarketIndex PARSEC / / OperatingSystem Linux / / Organization University of California / Berkeley / ASIC / Parallel Computing Laboratory CS Division / EECS Department / / Person Sarah Bird / Henry Cook / Andrew Waterman / Cadence Palladium / Verification / David Patterson / Krste Asanovi / / Position General / OS scheduler / Model / designer / Exception/Write Back RX Thread Scheduler / representative / scheduler / memory controller / Controller / / Product 3a Experimental Setup Our / / ProgrammingLanguage R / Ruby / / ProvinceOrState Manitoba / FPGA CAD / / Technology FPGA / RAM / chip design / Opteron processors / Linux / System-on-a-Chip / multicore processors / operating system / out-oforder superscalar processor / shared memory / operating systems / out-of-order superscalar processors / CMP / target processor / Research processors / ASIC / target processors / manycore processors / OS page-coloring algorithm / data mining / 16 on-chip routers / simulation / animation / final target technology / sequential consistency / DSP / Flash / Flash memory system / parallel processing / Gigabit Ethernet / CAD / now developed working FPGA / / URL http / SocialTag 
A Case for FAME: FPGA Architecture Model Execution Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovi´c, David Patterson The Parallel Computing Laboratory CS Division, EECS Department, University of Cal