| Document Date: 2010-09-27 14:41:05
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City Incremental Block / / Company I. I NTRODUCTION Modern / C.Y. Cho D.D. / F. Rigaud / on Semiconductor Manufacturing / Sandisk Inc. / IEEE Intl / Y. / / / Event Product Issues / / Facility Kcell library / Nangate Open Cell library / University of California / synthesized using 45nm Nangate Open Cell library / / IndustryTerm metal / metal wires / back-end-of line manufacturing cost / large manufacturing / incurred processing cost / manufacturing/test costs / neural network / back-end-of-line manufacturing cost / manufacturing costs / interconnect metal layers / defective chips / back-end-of-line manufacturing costs / back-end manufacturing / manufacturing cost / manufacturing / path selection algorithms / metal layers / / Organization ASIC / National Science Foundation / University of California / Los Angeles / SRC / Department of Electrical Engineering / / Person C. Spanos / R.S. Ghaida / H. Kim D.Y. Lim / Monte-Carlo Spice / L. Cheng / P. Gupta / L. He / K. Qian / T.B. Chan / / Position RT / representative / Cao / / Product Ief / chips / / ProvinceOrState California / / Technology path selection algorithms / Expected profit =Expected good chips / defective chips / 0.72 0.74 0.76 0.78 Chip / ASIC / neural network / 0.25um CMOS Technology / 657 chips / simulation / process control / Integrated Circuits / CAD / / URL http /
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Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction Tuck-Boon Chan∗ , Aashish Pant∗ , Lerong Cheng† , Puneet Gupta∗ {tuckie,apant,puneet}@ee.ucla.edu, [removed], ∗ Depa