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Processor-in-memory
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1	White Paper Intel® Xeon® Processor Big Data Management Terracotta and Intel: Breaking Down Barriers to In-memory Add to Reading List Source URL: www1.softwareag.com - Date: 2017-12-28 04:03:54
2	Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks-0.4cm Add to Reading List Source URL: iacoma.cs.uiuc.edu - Date: 2017-08-27 00:30:38
3	Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks Aditya Agrawal, Josep Torrellas and Sachin Idgunji University of Illinois at Urbana Champaign and Nvidia Corporation http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu - Date: 2017-12-03 00:14:18
4	1 Underdesigned and Opportunistic Computing in Presence of Hardware Variability Puneet Gupta1 , Member, IEEE, Yuvraj Agarwal2 , Member, IEEE, Lara Dolecek1 , Member, IEEE, Nikil Dutt6 , Fellow, IEEE, Rajesh K. Gupta2 , Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2012-09-17 19:39:16 Engineering Computing Technology Parallel computing Computer memory Electronic design Electronic engineering Integrated circuit design Embedded system Multi-core processor Error detection and correction Software
5	Design Issues in Parallel Array Languages for Shared Memory ! James Brodman1 , Basilio B. Fraguela2 , Mar´ıa J. Garzar´an1 , and David Padua1 1 University of Illinois at Urbana-Champaign, Dept. of Computer Science Add to Reading List Source URL: polaris.cs.uiuc.edu Language: English - Date: 2008-06-04 16:32:10 Parallel computing Computing Computer programming Software engineering Data parallelism SPMD HTML Application Stream processing Task parallelism OpenMP Multi-core processor Thread
6	Servet: A Benchmark Suite for Autotuning on Multicore Clusters Jorge Gonz´alez-Dom´ınguez, Guillermo L. Taboada, Basilio B. Fraguela, Mar´ıa J. Mart´ın, Juan Touri˜no Computer Architecture Group Department of Ele Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2010-07-14 07:49:10 Computing Computer architecture Computer engineering Cache Computer memory Cache hierarchy Multi-core processor Xeon Memory hierarchy Intel Core CPU cache Cache memory
7	Parallel and distributed computing in the multi-core and chip multi-processor system era Leonel Sousa, TU Lisbon Add to Reading List Source URL: sips.inesc-id.pt Language: English - Date: 2008-12-13 04:54:45 Computing Parallel computing Chaves Portugal University of Trs-os-Montes and Alto Douro Vila Real Portugal Multi-core processor Transactional memory INESC-ID Instituto Superior de Engenharia do Porto
8	hwloc: a Generic Framework for Managing Hardware Affinities in HPC Applications Fran¸cois Broquedis, J´erˆome Clet-Ortega, St´ephanie Moreaud, Nathalie Furmento, Brice Goglin, Guillaume Mercier, Samuel Thibault, Raym Add to Reading List Source URL: hal.inria.fr Language: English - Date: 2016-06-17 14:31:53 Computing Computer architecture Parallel computing Message Passing Interface Multi-core processor CPU cache Opteron Zen Thread Multiprocessing Multithreading Draft:Cache memory
9	Hierarchical Parallelism in a Partitioned Address Space Model Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2012-07-27 09:37:34 Parallel computing Partitioned global address space Manycore processor Non-uniform memory access PGAS SPMD XC Pointer Cell Pascal Barrier
10	Lecture Notes: Memory Systems Rajeev Balasubramonian March 29, DRAM vs. SRAM On a processor chip, data is typically stored in SRAM caches. However, an SRAM cell is large enough Add to Reading List Source URL: www.eng.utah.edu Language: English - Date: 2013-10-28 19:14:05

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