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Xilinx / Field-programmable gate array / Delay-locked loop / Joint Test Action Group / Programmable logic device / Flip-flop / Pull-up resistor / Logic level / Electronic engineering / Electronics / Digital electronics


DS003: Virtex™ 2.5V Field Programmable Gate Arrays (Complete)
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Document Date: 2013-04-01 16:46:23

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File Size: 739,20 KB

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Company

Xilinx Inc. / Alliance Development Systems / See I/O Banking / Product Specification Bank / GCLK1 GCLK0 Bank / GCLK3 GCLK2 Bank / /

Facility

Plastic Quad Flat Pack HQ / Port Block SelectRAM Table / /

IndustryTerm

place-and-route software / metal / larger devices / capacity programmable logic solution / bank pairs / process technology / larger device / bank / given bank / WEB ENB RSTB CLKB / given device / capacity programmable logic solutions / bank affiliation / metal process / /

Organization

Xilinx Foundation / FPGA Foundation / /

Person

LUT XQ DI REV / Weak Keeper SR / PAD D Q CE OBUFT SR / ENA RSTA CLKA / /

/

Position

Manager - Wide selection / Design Manager / output driver / representative / /

Product

GCLK3 GCLK2 Bank 2 A / /

ProgrammingLanguage

RC / EC / /

Technology

FPGA / RAM / WSH / 36 6.9 ns Chip-to-Chip / JTAG / SRAM / simulation / process technology / DSP / /

URL

http /

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