Delay-locked loop

Results: 16



#Item
1614  IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 4, APRIL 2003 Jitter Transfer Characteristics of Delay-Locked Loops—Theories and Design Techniques

614 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 4, APRIL 2003 Jitter Transfer Characteristics of Delay-Locked Loops—Theories and Design Techniques

Add to Reading List

Source URL: cva.stanford.edu

Language: English - Date: 2005-12-01 13:38:05
2NETWORKS  Principles of Robust Timing over the Internet The key to synchronizing clocks over networks is taming delay variability. Julien Ridoux and Darryl Veitch, University of Melbourne

NETWORKS Principles of Robust Timing over the Internet The key to synchronizing clocks over networks is taming delay variability. Julien Ridoux and Darryl Veitch, University of Melbourne

Add to Reading List

Source URL: www.cubinlab.ee.unimelb.edu.au

Language: English - Date: 2010-04-18 18:38:25
31804  IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002 A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly

1804 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002 A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly

Add to Reading List

Source URL: cva.stanford.edu

Language: English - Date: 2005-12-01 13:38:05
4[removed]On-Board Data Processing Part Time-Comparison-Equipment Processing Unit (TCE-PRO) KIUCHI Hitoshi, IMAE Michito, TAKAHASHI Yasuhiro, GOTOH Tadahiro, NAKAGAWA Fumimaru, FUJIEDA Miho, and HOSOKAWA Mizuhiko In satelli

[removed]On-Board Data Processing Part Time-Comparison-Equipment Processing Unit (TCE-PRO) KIUCHI Hitoshi, IMAE Michito, TAKAHASHI Yasuhiro, GOTOH Tadahiro, NAKAGAWA Fumimaru, FUJIEDA Miho, and HOSOKAWA Mizuhiko In satelli

Add to Reading List

Source URL: www.nict.go.jp

Language: English - Date: 2013-11-20 21:55:30
5Systems Involving Group Delay

Systems Involving Group Delay

Add to Reading List

Source URL: www.vmsk.org

Language: English - Date: 2006-03-05 14:40:36
6Digital electronics / Integrated circuits / Sigmaquad / Delay-locked loop / Electronic engineering / Electronics / Computer memory

AN1021 SigmaQuadTM and SigmaDDRTM Power-Up Introduction The SigmaQuadTM and SigmaDDRTM family of SRAMs, including Type-II, Type-II+, and Type IIIe, include a DLL (Delay Locked Loop) for output timing control. The DLL sy

Add to Reading List

Source URL: www.gsitechnology.com

Language: English - Date: 2013-12-10 07:45:29
7Preliminary AN1013 SigmaQuad Separate I/O Design Guide Introduction

Preliminary AN1013 SigmaQuad Separate I/O Design Guide Introduction

Add to Reading List

Source URL: www.gsitechnology.com

Language: English - Date: 2013-12-10 07:45:29
8AN1012  SigmaQuad Type I vs. Type II Timing Comparison Introduction SigmaQuad-II SRAMs implement a DLL (Delay Locked Loop). The DLL provides a larger data valid window by synchronizing the output data to the input clocks

AN1012 SigmaQuad Type I vs. Type II Timing Comparison Introduction SigmaQuad-II SRAMs implement a DLL (Delay Locked Loop). The DLL provides a larger data valid window by synchronizing the output data to the input clocks

Add to Reading List

Source URL: www.gsitechnology.com

Language: English - Date: 2013-12-10 07:45:29
9Preliminary AN1010 SigmaQuad Common I/O Design Guide Introduction

Preliminary AN1010 SigmaQuad Common I/O Design Guide Introduction

Add to Reading List

Source URL: www.gsitechnology.com

Language: English - Date: 2013-12-10 07:45:29
10Spartan-6 FPGA Clocking Resources User Guide

Spartan-6 FPGA Clocking Resources User Guide

Add to Reading List

Source URL: www.xilinx.com

Language: English - Date: 2013-10-19 02:48:48