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#	Item
1	AN1021 SigmaQuadTM and SigmaDDRTM Power-Up Introduction The SigmaQuadTM and SigmaDDRTM family of SRAMs, including Type-II, Type-II+, and Type IIIe, include a DLL (Delay Locked Loop) for output timing control. The DLL sy Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Digital electronics Integrated circuits Sigmaquad Delay-locked loop Electronic engineering Electronics Computer memory
2	Preliminary AN1017 SigmaQuad-IIIe Input Clocking Schemes KD and KD Input Clocks In previous industry-standard synchronous SRAMs (e.g., Burst SRAMs, NBT™ SRAMs, SigmaQuad/DDR/QDR™ -I/-II/-II+ Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Electronics Clock signal Electromagnetism Electrical engineering Quad Data Rate SRAM Computer memory Sigmaquad Flip-flop
3	Preliminary AN1013 SigmaQuad Separate I/O Design Guide Introduction Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Computer hardware Sigmaquad Flip-flop Clock signal Delay-locked loop Quad Data Rate SRAM Synchronous dynamic random-access memory Computer memory Electronic engineering Electronics
4	Preliminary AN1019 SigmaQuad-II+ and SigmaDDR-II+ On-Die Termination (ODT) Introduction When an electrical signal is transmitted along a transmission line, it is reflected back when it reaches the end of the line. That Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Computer buses Sigmaquad SDRAM On-die termination DDR2 SDRAM Q-Bus Computer memory Computer hardware Computing
5	SQ3e CIO-B2 DQ ODT Control.xls Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Sigmaquad Controller Computer memory On-die termination Semiconductors
6	Preliminary AN1023 SigmaQuad/DDR IIIe/IVe SRAM Overview Introduction Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Sigmaquad Computer memory SDRAM DDR3 SDRAM
7	AN1014 tKCvar Specification Introduction The tKCvar specification on SigmaQuad™ Type II/II+ and SigmaDDR™ Type II/II+ SRAMs describes two key clock performance requirements. The first addresses the reality that the Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Horology Clock Second Measurement Synchronization Jitter
8	AN1012 SigmaQuad Type I vs. Type II Timing Comparison Introduction SigmaQuad-II SRAMs implement a DLL (Delay Locked Loop). The DLL provides a larger data valid window by synchronizing the output data to the input clocks Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Oscillators Delay-locked loop Computer memory Sigmaquad Electronic engineering Electronics Electronic design
9	Preliminary AN1010 SigmaQuad Common I/O Design Guide Introduction Add to Reading List Source URL: www.gsitechnology.com Language: English - Date: 2013-12-10 07:45:29 Sigmaquad Computer hardware NOP Delay-locked loop Clock signal Quad Data Rate SRAM Synchronous dynamic random-access memory Computer memory Electronic engineering Electronics