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Integrated circuits / Electronic design / Placement / Logic synthesis / Field-programmable gate array / Jason Cong / Complex programmable logic device / Application-specific integrated circuit / Electronic engineering / Electronics / Electronic design automation


An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu
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Document Date: 2005-07-16 00:13:15

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File Size: 86,35 KB

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Company

Fujitsu / Case / MVSIS Group / Intel / /

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Event

Force Majeure / /

Facility

ECE University of Massachusetts / EECS University of California / /

IndustryTerm

technology mapping flow / technology mapping environment / software implementation / technology mapping / combinational networks / proposed technology mapping environment / technology mapping algorithms / depth-optimal area optimization mapping algorithm / combinational network / technology mapping algorithm / software prototype / http /

OperatingSystem

Windows XP / Linux / /

Organization

MARCO Focus Center for Circuit System Solution / ASIC / National Science Foundation / UC Berkeley / University of California / Berkeley / University of Massachusetts / Amherst / Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department / Univ. of California / Maciej Ciesielski Department / /

Person

Robert Brayton / Jason Cong / Deming Chen / Maciej Ciesielski / Alan Mishchenko Satrajit Chatterjee Robert / /

ProvinceOrState

California / /

Technology

FPGA / RAM / ASIC / minimumarea FPGA technology / same basic algorithm / Linux / proposed technology / 3 Technology / LUT FPGA technology mapping algorithm / area optimization mapping algorithm / simulation / technology mapping algorithm / retiming-based technology mapping algorithm / technology mapping algorithms / FPGA technology / LUT-based FPGA technology / CAD / using the same basic algorithm / /

URL

http /

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