| Document Date: 2005-05-01 15:17:53
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Company Fujitsu / Ford / AIG / Intel / / / Facility Computer Sciences University of California / SC library / / IndustryTerm incremental placement algorithm / libraryless technology / integrated technology mapping environment / intermediate networks / heuristic algorithm / technology mapping / combinational networks / binary search / logic synthesis algorithms / depth-optimal area optimization mapping algorithm / technology mapping step / technology mapping algorithm / final mapped network / final network / cyclic network / cross-product / technology mapper / mapped network / individual search spaces / sequential networks / / Organization MARCO Focus Center for Circuit System Solution / National Science Foundation / UC Berkeley / University of California / Berkeley / / Person A. Kuehlmann / V / Jie-Hong Jiang Robert Brayton / Alan Mishchenko Satrajit Chatterjee / / Position manager / the appropriate register markings / RT / FRAIG manager / / Product Pan / / Technology The technology / FPGA / integrated technology / DSM technologies / integrated algorithm / incremental placement algorithm / period FPGA technology / performanceoptimal FPGA technology / logic synthesis algorithms / area optimization mapping algorithm / Simulation / technology mapping algorithm / retiming-based technology mapping algorithm / Wavefront technology / CAD / /
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Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Jie-Hong Jiang