LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan - Programmable Array Logic - Document - PDFSEARCH.IO

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	LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan Add to Reading List Document Date: 2009-07-09 02:20:06 Open Document File Size: 385,76 KB Share Result on Facebook City Princeton / New Orleans / Dana Point / A PC / Lake Tahoe / Boston / / Company D. Van Nostrand Co. / ABC / Computer Sciences / Intel / Altera / / Country United States / / Currency pence / / Facility Kyushu Institute of Technology / University California Berkeley / / IndustryTerm logical product / logic networks / reconfigurable hardware / minimal solutions / technology mapping / logic synthesis algorithms / optimum solutions / sum-of-products / last post-processing step / / MarketIndex MCNC / / MusicGroup ABC / / Organization Kyushu Institute of Technology / / Person A. Mishchenko / S. Chatterjee / Tsutomu Sasao / Alan Mishchenko / R. K. Brayton / / ProvinceOrState New Jersey / Louisiana / California / / PublishedMedium IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems / / Technology FPGA / 5 Experimental Results Algorithm / RAM / logic synthesis algorithms / Integrated Circuits / LUT-based FPGA technology / / URL http / SocialTag Boolean algebra Diagrams Field-programmable gate array Binary decision diagram Lookup table Xilinx Multiplexer Artificial neuron Function Computing

LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], JapanAdd to Reading List