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Digital electronics / Integrated circuits / Standard cell / Field-programmable gate array / Logic optimization / Retiming / Physical design / Logic synthesis / Placement / Electronic engineering / Electronic design automation / Electronic design


Magic: An Industrial-Strength Logic Optimization, Technology Mapping, and Formal Verification System Alan Mishchenko Niklas Een Robert Brayton Stephen Jang Maciej Ciesielski
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Document Date: 2010-03-19 22:25:46

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File Size: 177,40 KB

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Company

Synopsys / ABC / RTL / AIG / /

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Facility

EECS LogicMill Technology Abound Logic University of California / /

IndustryTerm

industrial tool / verification solutions / technology mapping / public domain tool / real-time observability / research / delayoptimal technology / optimization tool / synthesis tool / software development / technology transfer / /

Organization

ASIC / University of California / Berkeley / EECS LogicMill Technology Abound Logic University / Industrial-Strength Logic Optimization / Technology Mapping / and Formal Verification System Alan Mishchenko Niklas Een Robert Brayton Stephen Jang Maciej Ciesielski Thomas Daniel Department / /

Person

Robert Brayton Stephen Jang / LUT FF / Brayton Stephen Jang Maciej / Stephen Jang Maciej Ciesielski Thomas Daniel / /

Position

researcher / engineer / /

Product

Magic / /

ProgrammingLanguage

Verilog / /

Technology

FPGA / ASIC / FGPA technology / Verilog / 3.1 Algorithms / CAD system / simulation / VHDL / LUT-based technology / CAD / using Verilog / verified using sequential simulation / /

URL

http /

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