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Electronic design / Integrated circuits / Fabless semiconductor companies / Field-programmable gate array / Logic synthesis / High-level synthesis / Timing closure / Altera / Integrated circuit design / Electronic engineering / Electronics / Electronic design automation


Datasheet Synplify Premier Fast, Reliable FPGA Implementation and Debug Overview
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Document Date: 2015-04-17 18:15:23


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File Size: 274,46 KB

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Company

HDL / Microsemi / Altera / RTL / Synopsys Inc. / Lattice Semiconductor / Xilinx / /

Country

United States / /

Facility

Building Block IP / /

IndustryTerm

logic synthesis algorithms / technology timing estimation / synthesis tool / design technology / point technology / programmable devices / design power optimization algorithms / path-group technology / /

Organization

FPGA / ASIC / /

Person

Fast / Features Benefits / Locate / Features Benefits All / /

Position

Datasheet Synplify Premier / The Synplify Premier / Physical Analyst / Synplify Premier product flow / Synplify Premier / Analyst / /

Product

Debugger / HAPS / /

ProgrammingLanguage

Verilog / /

Technology

FPGA / RAM / ASIC / design power optimization algorithms / Verilog / design technology / logic synthesis algorithms / simulation / point technology / DSP-aware mapping technology / DSP / VHDL / /

URL

www.synopsys.com / www.synopsys.com/FPGA / http /

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