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	Microsoft Word - power18.doc Add to Reading List Document Date: 2009-07-10 18:57:40 Open Document File Size: 105,93 KB Share Result on Facebook Company IBM / ABC / Mapping Stephen Jang Kevin Chung Xilinx Inc. / Altera / AIG / 3M / Actel / Mentor Graphics / Synopsys / Intel / Xilinx / / / Facility University of California / / IndustryTerm structural technology / logic network / by-product / synergistic algorithms / background on logic synthesis and technology / power-optimization algorithms / integrated technology / power-aware technology / technology mapper / resynthesis algorithm / basic algorithm / power-aware logic optimization algorithms / semiconductor device / logic networks / priority-cut based technology / decisions during technology / recent technology mapper / wire-aware technology / / MusicGroup ABC / / Organization National Science Foundation / Alan Mishchenko Robert Brayton Department of EECS / University of California / Berkeley / / Person Alan Mishchenko Robert Brayton / / Position hb / manager / representative / / Product DeMorgan / Estimator User Guide / / Technology semiconductor / FPGA / two synergistic algorithms / RAM / 5 Experimental Results The algorithms / FGPA technology / priority-cut based technology / power-aware technology / power-optimization algorithms / resynthesis algorithm / pdf / FPGA technology / LUT-based FPGA technology / wire-aware technology / integrated technology / 2.3 Technology / 4.1 Technology / power-aware logic optimization algorithms / simulation / basic algorithm / CAD / / URL http / SocialTag Electronic design Integrated circuits And-inverter graph Field-programmable gate array Logic synthesis Logic gate Sequential logic Power optimization CMOS Electronic engineering