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Central processing unit / Microprocessors / Computer memory / CPU cache / Cache / Runahead / Multi-core processor / Microarchitecture / Memory-level parallelism / Computer hardware / Computer architecture / Computing


Scalable Cache Miss Handling for High Memory-Level Parallelism
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Document Date: 2006-10-02 23:12:53

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File Size: 1,29 MB

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Company

Checkpoint / Hierarchical / IBM / Banked Current Unified Banked Hierarchical Unlimited / Cache MSHR File Processor L1 Bank / SPECfp2000 / Bank L1 Bank MSHR / Same Area MHAs / GM / L1 Bank / Bank L1 Bank Dedi / Intel / /

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Event

Company Expansion / /

Facility

We pipeline / Store Queue State / Josep Torrellas University of Illinois / /

IndustryTerm

nanoscale technologies / bank access conflict / cross-bank access imbalances / per-bank files / heavy banking / concurrent applications / bank / replacement algorithm / identical memory systems / 65nm technology / banking / low per-bank capacity / file replacement algorithm / bank lock-up / bank locks-up / memory systems / highMLP processor / /

Organization

MSHRs Assoc. / University of Illinois / Overall Organization / National Science Foundation / Status Holding Register / Ded / SESC / /

Person

Luis Ceze / Time Size (Bytes) / Handling Architectures / James Tuck / /

Product

L1 / Franklin / /

ProgrammingLanguage

FP / Fortran 90 / C++ / /

ProvinceOrState

Oregon / /

Technology

high-MLP processor / nanoscale technologies / three processors / Conventional processors / Dedicated file replacement algorithm / LargeWindow processor / Conventional processor / relatively low-MLP processors / Checkpointed processor / high-MLP processors / LargeWindow processors / 65nm technology / 5-issue / 2-context SMT processor / SMT processors / Checkpointed processors / highMLP processor / FIFO replacement algorithm / /

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