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Are We Ready for High Memory-Level Parallelism? Luis Ceze, James Tuck and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign Email: {luisceze,jtuck,torrella}@cs.uiuc.edu
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Document Date: 2006-02-06 00:34:38

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City

New York / Washington / DC / /

Company

Checkpoint / Current Unified Banked Unlimited / L1 Bank MSHR / ACM Press / Intel Corp. / IEEE Computer Society Press / Compaq Western Research Laboratory / Current (a) Checkpointed Current Unified Banked Unlimited / IBM Corp. / GM / L1 Bank / /

Country

United States / /

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Facility

University of Illinois / Checkpoint Assisted VAlue Prediction / Store Queue State / Computer Science University of Illinois / Checkpoint Processing / Store Queue / /

IndustryTerm

latency tolerant processors / heavy banking / cache bank / cache banking / latency-tolerant processors / plain large-window processor / costly global search / store processing / bank / identical memory systems / latency-tolerate processors / cache coherence protocol / /

OperatingSystem

Microsoft Windows / /

Organization

Explicit / Implicit / University of Illinois / Josep Torrellas Department / IEEE Computer Society / Lockup-Free Instruction Fetch/Prefetch Cache Organization / /

Person

Luis Ceze / S. T. Srinivasan / Max Outs / Addison Wesley / Mike Upton / Handling Architectures / K. Lai / H. Akkary / A. Gandhi / R. Rajwar / Handling An / Karin Strauss / James Tuck / /

Position

RT / head / 10GB/s Mem RT / /

Product

SPECfp2000 / L1 / Franklin / SPECint2000 / /

ProgrammingLanguage

FP / Fortran 90 / DC / /

ProvinceOrState

Illinois / /

Technology

three processors / 4 Processor / plain large-window processor / Checkpointed processor / High ILP Processors / Out-of-order Processors / Large Instruction Window Processors / Processor L1 Cache MSHR File Processor / cache coherence protocol / Operating Systems / Simultaneous Multithreading Processor / latency-tolerate processors / MHA algorithms / 90nm Technology / latency-tolerant processors / Out-of-order Commit processors / 5-issue / 2-context SMT processor / SMT processors / latency tolerant processors / high MLP processors / /

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