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21	Synopsys Professional Services Datasheet Design Flow Deployment At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:39:43 Integrated circuits Electronic design Digital electronics Synopsys Timing closure Integrated circuit design Design flow Signoff EDA database Electronic engineering Electronics Electronic design automation
22	Datasheet NanoTime Transistor-level Static Timing Analysis Solution for Custom Designs Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-27 00:06:11 Signoff Synopsys Static timing analysis Signal integrity Electronic circuit simulation Delay calculation Logic simulation Parasitic extraction SPICE Electronic engineering Electronic design automation Digital electronics
23	Datasheet IC Validator Overview IC Validator is a signoff DRC / LVS Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-04-22 17:53:38 Design Signoff Design rule checking Integrated circuit layout Physical design Design closure Tape-out Synopsys Physical verification Electronic engineering Electronic design automation Electronic design
24	Datasheet Galaxy Custom Designer LE Custom Layout Editing Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:29:15 Electronic design automation Design rule checking Process design kit Application-specific integrated circuit Integrated circuit design Signoff Electronic engineering Electronics Integrated circuits
25	White Paper Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform February 2014 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:38 Timing closure Physical design Design closure Integrated circuit design Static timing analysis ECO Synopsys Signal integrity Design rule checking Electronic engineering Electronic design automation Signoff
26	Synopsys Professional Services Datasheet Tool and Methodology Consulting At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:40:16 Signoff SystemVerilog Power optimization EDA database Timing closure Electronic engineering Electronic design automation Synopsys
27	Datasheet Formality and Formality Ultra Equivalence Checking for DC Ultra and Design Compiler Graphical Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 15:15:30 Formal methods Physical design SystemVerilog Synopsys Formal verification Verilog Formal equivalence checking Signoff Electronic engineering Electronic design automation Hardware description languages
28	Datasheet SiliconSmart Comprehensive Cell, I/O and Memory Characterization Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:38 Standard cell Signoff SPICE Verilog Electronic circuit simulation Synopsys Signal integrity Simucad Electronic engineering Electronic design automation Digital electronics
29	Datasheet IC Compiler Comprehensive Place and Route System Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-03-05 12:15:39 Integrated circuits Electronic design Digital electronics Signoff Timing closure Physical design Design closure Integrated circuit design Compiler Electronic engineering Electronic design automation Electronics
30	Datasheet Sysnav CAD Navigation for Printed Circuit Boards, Multi-Chip Modules, and Stacked Die Applications Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-03-24 11:15:52 Hillsboro Oregon Synopsys Electronic design automation Printed circuit board Signoff EDA database Electronic engineering Electromagnetism Electronics