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Semiconductor device fabrication / Electronics manufacturing / Ball grid array / Integrated circuit packaging / Capacitor / Flip chip / Bumpless Build-up Layer / Integrated circuit / Chip scale package / Technology / Electronics / Electronic engineering


Document Date: 2001-12-06 18:32:34

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City

Santa Clara / Garner / New York / Las Vegas / Wiley / /

Company

Gilroy J. Vandentop Intel Corporation / Chickamenahalli S. A. / ANSYS / Sigrity Inc. / IEEE Press / BBUL / Intel / inductance Lp / Cd (6) 1 Lp C / /

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IndustryTerm

thermal solutions / on-die core devices / realistic device / final products / technology requirements / circuit board applications / microelectromechanical systems / logic chips / thermal energy / circuit technology advances / nm generation silicon technology / package processing / package technology / semiconductor device / materials on-chip / flip-chip / thermal systems / build-up technology / silicon process technology / test chip / logic technology / thermal and socketing solution / µm generation process technology / /

NaturalFeature

Kohala Coast / /

Person

Cornelius / Kodali / V / Richard D. Emery / Henning Braunisch / Chuan Hu / Steven N. Towle / /

Position

VRM model / ” Proc / V. P. / /

ProvinceOrState

New York / South Dakota / Arizona / /

Region

Pacific Rim / /

Technology

semiconductor / silicon process technology / 0.13 µm generation process technology / 65 nm generation silicon technology / logic technology / build-up technology / integrated circuit technology / Test chip / laser / microelectromechanical systems / MEMS / proposed CSP technologies / flip-chip Controlled Collapsed Chip / package technology / dielectric / logic chips / radio frequency / simulation / materials on-chip / /

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