![Computer engineering / CPU cache / Microarchitecture / Speculative execution / Processor register / Application checkpointing / Parallel computing / Instruction set / Multithreading / Computer architecture / Computer hardware / Central processing unit Computer engineering / CPU cache / Microarchitecture / Speculative execution / Processor register / Application checkpointing / Parallel computing / Instruction set / Multithreading / Computer architecture / Computer hardware / Central processing unit](https://www.pdfsearch.io/img/a131bedc7a966dcacb4085a64b5df25e.jpg) Date: 2005-05-11 13:27:29Computer engineering CPU cache Microarchitecture Speculative execution Processor register Application checkpointing Parallel computing Instruction set Multithreading Computer architecture Computer hardware Central processing unit | | Prototyping Architectural Support for Program Rollback Using FPGAs ∗ Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {teodores,torrellas}@cs.uiuc.eduAdd to Reading ListSource URL: iacoma.cs.uiuc.eduDownload Document from Source Website File Size: 186,32 KBShare Document on Facebook
|