| Document Date: 2005-05-11 13:27:29
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City Austin / / Company Checkpoint / IBM / IACOMA / ACM Press / PROBE / Xilinx / Intel / / Country Jordan / / / Event Product Issues / / Facility port RAM / In CHECKPOINT / Computer Science University of Illinois / port RAMs / / IndustryTerm lightweight software / larger debugging infrastructure / software approach / larger infrastructure / parallel applications / target technology / software reliability / software bugs / production software / buggy applications / long-running applications / rollback/replay systems / system-on-a-chip infrastructure / / OperatingSystem UNIX / Linux / Microsoft Windows / / Organization Radu Teodorescu and Josep Torrellas Department / National Science Foundation / University of Illinois / IEEE Computer Society / / Person Jun Nakano / Brian Greskamp / Paul Sack / / Position cache controller / synthesizable SDRAM controller / write-back cache controller / synthesizable SDRAM controller / PCI and Ethernet interfaces / controller / programmer / / Product LEON2 / code / / ProvinceOrState Texas / Illinois / / TVStation Kbit / / Technology FPGA / FPGA chip / RAM / SPARC V8 processor / Linux / UNIX / modified processor / system-on-a-chip / FPGA system / SRAM / operating system / Leon2 processor / 1.2 Technology / Operating Systems / VHDL / FPGA technology / Ethernet / existing processor / target FPGA chip / target technology / Virtex-II FPGA chip / Multiscalar Processors / SDRAM / FLASH / UART / / URL www.gaisler.com / www.pender.ch / www.snapgear.org / /
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Prototyping Architectural Support for Program Rollback Using FPGAs ∗ Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {teodores,torrellas}@cs.uiuc.edu