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Superscalar
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#	Item
91	--12 February 12, 2001 Hamal Design Rationale J.P. Grossman Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2001-05-16 17:41:23 Central processing unit Parallel computing Supercomputers Microprocessors Very long instruction word Instruction set Superscalar 64-bit Processor register Computer architecture Computing Computer hardware
92	Compiler and Architectural Techniques for Improving the Effectiveness of VLIW Compilation J.P. Grossman Abstract Effective VLIW compilation requires optimizing across basic block boundaries. In this mildly opinionated pa Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2000-04-28 16:10:10 Parallel computing Computer engineering Compiler construction Very long instruction word Trace scheduling Software pipelining Branch predication Superscalar Instruction-level parallelism Computing Computer architecture Compiler optimizations
93	Microsoft PowerPoint - Arakawa-Figs-2.ppt [Compatibility Mode] Add to Reading List Source URL: media.wiley.com Language: English - Date: 2013-08-30 13:15:06 Instruction set architectures Microprocessors Parallel computing Classes of computers Multi-core processor MIPS architecture SuperH DEC Alpha Superscalar Computer architecture Computing Computer hardware
94	parently reordering instructions from nearby program regions, but even sophisticated compiler scheduling is fundamentally limited by the compiler’s inability to perfectly determine the programmer’s intent and its com Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:40 Parallel computing Microprocessors Threads Central processing unit Simultaneous multithreading Multi-core processor Multithreading Instruction-level parallelism Superscalar Computing Computer hardware Computer architecture
95	Microsoft Word - cn_architecture_brief.doc Add to Reading List Source URL: www.centtech.com Language: English - Date: 2009-09-09 16:18:50 Central processing unit Instruction set architectures VIA Nano X86 Pentium Pro Centaur Technology CPU cache Microcode Superscalar Computer architecture Computer hardware Computing
96	The Emotion Engine and Vector Unit Design Add to Reading List Source URL: www.cs.nyu.edu Language: English - Date: 2002-05-20 07:51:40 Central processing unit Parallel computing Classes of computers Microprocessors Emotion Engine SIMD Superscalar MIPS architecture Coprocessor Computer architecture Computer hardware Computing
97	QED RISCMark™ RM7000™ 64-Bit Superscalar Microprocessor Advanced Information Add to Reading List Source URL: www.futuretech.blinkenlights.nl Language: English - Date: 1999-05-14 11:00:58 Quantum Effect Devices CPU cache R5000 R4000 Cache Motorola 68000 family R8000 KOMDIV-64 Computer hardware Computer architecture MIPS architecture
98	SIMULATING SOME ADVANCED PROCESSING TECHNIQUES INTO A SUPERSCALAR ARCHITECTURE Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-05-17 01:41:51 Central processing unit Classes of computers Computer memory Parallel computing CPU cache Superscalar Cache Reduced instruction set computing Instruction-level parallelism Computer hardware Computer architecture Computing
99	IET Computers & Digital Techniques Multi-Objective Optimizations for a Superscalar Architecture Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2012-09-24 04:28:00 CPU cache Central processing unit Computing Computer memory Cache Computer hardware
100	Energy-Performance Design Space Exploration in SMT Architectures Exploiting Selective Load Value Predictions A. Gellert1 G. Palermo2 Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-02-24 17:04:56 Central processing unit Branch predictor CPU cache Microarchitecture Memory-level parallelism Register renaming Superscalar DEC Alpha Computer performance Computer architecture Computer hardware Computer engineering

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