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61	Emulex Enhances Design Productivity With Synopsys’ Advanced Verification Solutions “Emulex has built a strong working relationship with Synopsys over the past several years. Because of the confidence we’ve gained i Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:37:40 Hardware verification languages Electronic design automation SystemVerilog Emulex Electronic engineering Hillsboro Oregon Synopsys
62	Quick Reference for Verilog HDL  Add to Reading List Source URL: frank.harvard.edu Language: English - Date: 2004-03-30 19:59:24 Verilog E VHDL Logic synthesis SystemVerilog Electronic engineering Hardware description languages Electronic design automation
63	DeMicheli Spring[removed]EE271 Verilog According to Tom Add to Reading List Source URL: frank.harvard.edu Language: English - Date: 2004-03-30 19:59:35 Hardware verification languages Verilog Logic design SystemC E SystemVerilog Verilog-AMS Electronic engineering Hardware description languages Electronic design automation
64	Corporate Program Case Study IEEE-SA Electronic Design Automation (EDA) Standards A robust portfolio of critical standards evolves with the support of IEEE Corporate Standards Program Add to Reading List Source URL: standards.ieee.org Language: English - Date: 2011-07-19 11:40:08 IEEE standards Engineering Electrical engineering Accellera IEEE Standards Association Institute of Electrical and Electronics Engineers SystemVerilog IP-XACT IEEE Design Automation Standards Committee Standards organizations Electronic design automation Electronic engineering
65	White Paper Using Digital Verification Techniques on Mixed-Signal SoCs with CustomSim and VCS March 2011 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:39:04 Electronic design Verilog-AMS Electronic test equipment SystemVerilog Signal generator Analog verification Verilog E System on a chip Electronic engineering Hardware description languages Hardware verification languages
66	Technical Backgrounder CustomExplorer Ultra Automated Regression for Mixed-Signal Verification April 2011 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:40:27 Logic design Hardware description languages SystemVerilog Verilog SPICE Netlist Logic simulation Simucad Electronic engineering Electronic design automation Digital electronics
67	Solution Overview Custom and Mixed-Signal Design Solution Unified Solution for Custom and Cell-Based Design and Verification January 2012 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:28:38 Signoff Synopsys Waveform viewer Standard cell Design rule checking Physical design Electronic circuit simulation Parasitic extraction SystemVerilog Electronic engineering Electronic design automation Digital electronics
68	Datasheet VCS AMS Mixed-Signal Verification Solution Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-03-06 15:46:48 Verilog-AMS SystemVerilog Verilog-A Verilog Synopsys SystemC Functional verification E System on a chip Electronic engineering Hardware description languages Electronic design automation
69	Preface i SystemVerilog Assertions rd Add to Reading List Source URL: systemverilog.us Language: English - Date: 2012-09-03 22:27:59 Hardware description languages Logic in computer science SystemVerilog Verilog E Assertion Model checking Formal methods Formal verification Electronic engineering Electronic design automation Hardware verification languages
70	UVM Random Stability Don’t leave it to chance Avidan Efody Mentor Graphics, Corp. 10 Aba Eban Blvd. Add to Reading List Source URL: www.specman-verification.com Language: English - Date: 2012-04-06 06:45:51 Hardware description languages SystemVerilog Random number generation E Verilog Pseudo-ring Universal Verification Methodology University of Vermont Shuffling Electronic engineering Hardware verification languages Randomness

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