<--- Back to Details
| First Page | Document Content | |
|---|---|---|
 Date: 2013-12-19 04:43:37CPU cache Latency Cache Worst-case execution time Synchronous dynamic random-access memory Parallel computing Conventional PCI Dynamic random-access memory Computer hardware Computer memory Computing |
|
Timing Anomalies in Multi-core Architectures due to the Interference on the Shared Resources Hardik Shah, Kai Huang and Alois Knoll Department of Informatics VI, Technical University Munich, 85748 Garching, Germany. {sha