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Timing Anomalies in Multi-core Architectures due to the Interference on the Shared Resources Hardik Shah, Kai Huang and Alois Knoll Department of Informatics VI, Technical University Munich, 85748 Garching, Germany. {sha
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Document Date: 2013-12-19 04:43:37

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File Size: 1,43 MB

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City

Garching / /

Company

Altera / /

Country

Germany / /

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Event

Product Issues / /

Facility

pipeline etc / Technical University / /

IndustryTerm

real-time control applications / aggressive co-existing applications / evidences using real applications / model timing anomalous processor / search process resumes / scheduled processor / co-existing applications / /

MarketIndex

WCET / /

OperatingSystem

L3 / /

Organization

Technical University Munich / Alois Knoll Department / U.S. Securities and Exchange Commission / /

Person

Kai Huang / /

Position

shared resource arbiter / round robin arbiter / arbiter / shared bus arbiter / /

Product

behavior / /

ProvinceOrState

Alabama / /

TVStation

WCET / /

Technology

FPGA / Sdram / floating point unit / simulation / Tdma / operating system / shared memory / dynamically scheduled processor / model timing anomalous processor / /

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