| Document Date: 2007-09-19 14:31:14
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Company On-Chip Networks / Intel / / Currency pence / / / Facility William J. Dally Computer Systems Laboratory Stanford University / / IndustryTerm router services more processors / off-chip interconnection networks / torus network / client protocols / distant routers / lower energy consumption / system interconnection networks / energy inefficiency / certain routing algorithms / highradix routers / dimension2 routers / energy savings / radix off-chip interconnection networks / energy / active computing state / off-chip interconnection network / radix routers / interconnection network / conventional network / energy consumption / costand energy-efficient topology / low-radix networks / onchip networks / onchip network / conventional mesh network / flattened butterfly network / mesh network / minimal routing algorithm / interconnection networks / radix networks / butterfly network / 65nm technology / intermediate routers / energy efficiency / dimension1 routers / chip multiprocessor systems / minimal and non-minimal routing algorithms / mesh networks / / NaturalFeature Crossbar Channel / / Organization Stanford University / / Person William J. Dally / John Kim / James Balfour / / Position simple round-robin arbiter / arbiter / Mux Arbiter / yield arbiter / memory controller / / Product Teraflops research chip / Teraflops / / SportsLeague Stanford University / / Technology TRIPS processor / 4.1 Router / 3-D / Routing algorithms / destination router / minimal routing algorithm / how high-radix routers / same source router / client protocols / dimension1 routers / Teraflops research chip / shared memory / CMP / 1 Introduction Chip / VLSI technology / load balancing / flow control / high-radix routers / network routers / dimension2 routers / 8 routers / 65nm technology / RAW processor / receiving processor / simulation / network router / minimal and non-minimal routing algorithms / neighbouring routers / local router / routing algorithm / certain routing algorithms / radix-10 routers / nodes to/from R2 to/from R0 Router / /
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Flattened Butterfly Topology for On-Chip Networks John Kim, James Balfour, and William J. Dally Computer Systems Laboratory Stanford University, Stanford, CA 94305 {jjk12, jbalfour, dally}@cva.stanford.edu Abstract