31![IEEE TRANSACTIONS ON COMPUTERS, VOL. 40, NO. 9, SEPTEMBERExpress Cubes: Improving the Performance of k-ary n-cube Interconnection Networks IEEE TRANSACTIONS ON COMPUTERS, VOL. 40, NO. 9, SEPTEMBERExpress Cubes: Improving the Performance of k-ary n-cube Interconnection Networks](https://www.pdfsearch.io/img/d175c45bfca6533afc5e3f80626cf07f.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2008-04-03 14:17:54
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32![A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN. A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN.](https://www.pdfsearch.io/img/8fe4b9445d3877b6071582c30fc53563.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:04
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33![Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139 Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139](https://www.pdfsearch.io/img/2e5f967dec4e25349581c558ff87d3c6.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2008-04-03 14:20:06
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34![Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu](https://www.pdfsearch.io/img/de08b4d041c91d8d3f8d840e04211f58.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:04
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35![775 IEEE TRANSACTIONS ON COMPUTERS, VOL. 39, NO. 6, JUNE 1990 Performance Analysis of k-ary n-cube Interconnection Networks 775 IEEE TRANSACTIONS ON COMPUTERS, VOL. 39, NO. 6, JUNE 1990 Performance Analysis of k-ary n-cube Interconnection Networks](https://www.pdfsearch.io/img/9753997ad4e817a86aa0ade501f1fe29.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2008-04-03 14:18:56
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36![A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally](https://www.pdfsearch.io/img/5a3b7818b4b7de44938af9cda6347d53.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:05
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37![King Address March 2006 Richard P. Olenick In 1978 Andrei Voznesensky toured the United States providing Americans with a glimpse of Soviet life through his poetry readings. I was fortunate to be in one such audience whi King Address March 2006 Richard P. Olenick In 1978 Andrei Voznesensky toured the United States providing Americans with a glimpse of Soviet life through his poetry readings. I was fortunate to be in one such audience whi](https://www.pdfsearch.io/img/b458efbcf53724be4691b60c84db232d.jpg) | Add to Reading ListSource URL: phys.udallas.eduLanguage: English - Date: 2007-09-07 00:35:24
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38![In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. ppFlit-Reservation Flow Control Li-Shiuan Peh William J. Dally In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. ppFlit-Reservation Flow Control Li-Shiuan Peh William J. Dally](https://www.pdfsearch.io/img/5cac236d376ee6b02d9687d8341d0781.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:05
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39![Stanford University Concurrent VLSI Architecture Memo 124 Elastic Buffer Networks-on-Chip George Michelogiannakis∗, James Balfour and William J. Dally Concurrent VLSI Architecture Group Computer Systems Laboratory Stan Stanford University Concurrent VLSI Architecture Memo 124 Elastic Buffer Networks-on-Chip George Michelogiannakis∗, James Balfour and William J. Dally Concurrent VLSI Architecture Group Computer Systems Laboratory Stan](https://www.pdfsearch.io/img/3c03ec3ec9378fb7c2fe8e4e3fc3284e.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2008-08-26 22:57:32
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40![In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Jan, 2001, Monterrey, Mexico, ppBest Student Paper Award) A Delay Model and Speculative Architecture for Pip In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Jan, 2001, Monterrey, Mexico, ppBest Student Paper Award) A Delay Model and Speculative Architecture for Pip](https://www.pdfsearch.io/img/94ed0687c69069c886141285ae56bce4.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:04
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